Processors (e.g., microprocessors, CPUs, cores, etc.) are used in a wide variety of products and applications, from desktop computers to portable electronic devices, such as cellular phones, laptop computers, and PDAs (personal digital assistants). Some processors are extremely powerful (e.g., processors in high-end computer workstations), while other processors have a simpler design, for lower-end, less expensive applications and products.
There is a general dichotomy between performance and power. Generally speaking, high-performance processors having faster operation and/or more complex designs tend to consume more power than their lower-performance counterparts. Higher power consumption generally leads to higher operating temperatures and shorter battery life (for devices that operate from battery power). The ever-increasing demand and use of portable electronic devices is driving a demand to produce processors that realize lower-power operation, while at the same time maintaining satisfactory performance levels.
More than one clock can be internal to a computer system, including but not limited to: a CPU or core clock, a system bus clock, and a peripheral clock. A core clock dictates the speed at which the CPU or core in a computer system or a system on chip (SoC) operates. A system bus clock dictates the speed at which the system bus operates. A peripheral clock dictates the speed at which the peripheral or input/output (I/O) bus operates. These clocks can operate at different speeds because, for example, a CPU often operates at a faster speed relative to the system bus or a peripheral bus. As noted above, where high-speed performance is not required, lower clock speeds may be desirable for lower power consumption.
In systems where a synchronous clock is desirable or necessary, the clocks internal to a computer system are typically linked by being dependent upon the same clock source to derive a clock at the proper frequency. Further, the clocks are typically arranged in a cascading fashion, whereby the fastest clock derives its clock directly from an oscillator or other clock source, and the next fastest clock derives its clock from the fastest clock. In a non-limiting example of a computer system requiring a core clock, a system bus clock slower than the core clock, and a peripheral clock slower than the system bus clock, the core clock may be derived from the clock source by inputting the clock into a programmable divider circuit. The system bus clock may be derived from the core clock, and the peripheral clock may be derived from the bus clock. This cascading arrangement can be desirable for the system to maintain synchronization between the three clocks. FIG. 1 depicts the clock generation components of such an exemplary system.
Unfortunately, this arrangement may lead to wasted power. One scenario in which power can be wasted in a computer system relates to these one or more clocks internal to the computer system. As is known in the art, a computer system will generally consume more power at higher clock speeds, so while higher clock speeds often equate to higher performance, higher clock speeds also equate to higher power consumption, which is particularly relevant in battery-powered systems that need to balance speed and power for usability. As one non-limiting example of a scenario where power is wasted in a computer system, the CPU clock can be oscillating at its normal frequency when it is unnecessary, for example, when the CPU is waiting for an operation by a peripheral or system bus device to complete. In such a scenario, it is possible for a CPU to be performing little or no useful operations other than waiting for a peripheral or system bus device to complete an operation or return a result.
One solution for reducing the power consumption of a computer system involves reducing the frequency of a core clock when it is not necessary for the core clock to be oscillating at its normal frequency. However, in a computer system with a cascading arrangement of circuits designed to produce synchronous clocks, such as the aforementioned example, reducing the frequency of a core clock will also reduce the frequency of the system bus and peripheral clocks because they are derived from the core clock. In the abovementioned scenario where a CPU is waiting for a peripheral or bus operation to complete, this will result in lower performance of the system because the peripheral and system bus clocks would be slowed, despite the fact that the system bus and/or peripheral bus is busy conducting an operation.
Another drawback of reducing power consumption by reducing a core clock frequency during periods when a CPU is substantially idle is that for a system as in the aforementioned example depicted in FIG. 1, the programmable clock dividers used to derive a clock signal often require one or more instructions to configure. Reducing the core clock frequency to conserve power in such a system would require the execution of one or more instructions to reprogram a programmable clock divider to lower the clock frequency, and subsequently one or more instructions to resume the normal or higher speed clock frequency, which is a less than ideal proposition.
Accordingly, there is a heretofore unaddressed need to overcome the deficiencies and shortcomings described above.